Semiconductor integrated circuit device

ABSTRACT

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW 1  and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to semiconductorintegrated circuit devices and, more particularly, to layout schemes ofstatic random access memory (SRAM) cells. The invention also relates tosemiconductor memory devices using such cells.

[0002] One-port SRAM cells with complementary metal oxide semiconductor(CMOS) configurations are typically designed so that each cell consistsessentially of six separate transistors. An exemplary layout of suchcells has been disclosed in, for example, JP-A-10-178110 (laid open onJun. 30, 1998).

[0003] In the prior known SRAM cell layout, a semiconductive well regionof P type conductivity with inverters formed therein is subdivided intotwo subregions, which are disposed on the opposite sides of an N-typewell region while permitting a well boundary line to extend in adirection parallel to bit lines.

[0004] The quest for higher integration and ultra-fine patterningtechniques in modern memory devices requires optical exposure apparatusor equipment to decrease in wave length of beams used therein. To thisend, the equipment is designed to employ exposure beams of shorterwavelength, which have advanced from G line to I line, and further toexcimer laser. Unfortunately the requirements for micro-patterningarchitectures grows more rapidly than technological advance in trend ofshortening wavelengths in such equipment. In recent years, it isstrictly required that micropatterning is done with the minimumdevice-feature length that shrinks to less than or equal to thewavelength of an exposure beam used. This minimum feature lengthshrinkage would result in the layout of IC components-here, memorycells-becoming more complicated in planar shape, which must require theuse of irregular polygonal layout patterns including key-shapedcomponents, in order to achieve the intended configuration of on-chipcircuitry with enhanced accuracy. This makes it impossible or at leastvery difficult to microfabricate ultrafine layout patterns whiledisadvantageously serving as the cause of destruction of the symmetry ofmemory cells.

[0005] Regrettably the prior art approach is associated with a need tocurve or bend a diffusion layer into a complicated key-like shape forthe purpose of making electrical contact with a substrate of the P-typewell region. Thus, the prior art suffers from a problem as todegradation of the symmetrization of cell layout pattern, makingdifficult successful achievement of microfabrication architectures forhigher integration densities.

SUMMARY OF THE INVENTION

[0006] In accordance with one aspect of the present invention, asemiconductor device is provided which comprises a first inverterincluding a first N-channel metal oxide semiconductor (MOS) transistorand a first P-channel MOS transistor, a second inverter including asecond N-channel MOS transistor and a second P-channel MOS transistorwith an input terminal being connected to an output terminal of thefirst inverter and with an output terminal being connected to an inputterminal of said first inverter, a third N-channel MOS transistor havinga source connected to the output terminal of said first inverter and adrain connected to a first bit line and also a gate connected to a wordline, and a fourth N-channel MOS transistor having a source connected tothe output terminal of said second inverter and a drain connected to asecond bit line plus a gate connected to a word line, wherein the firstand third N-channel MOS transistors are formed in a first P-type wellregion, wherein the diffusion layer has no curved or bent portions whileletting the direction of layout be parallel to the boundary with respectto the first N-well region with the first and second P-channel MOStransistors formed therein, and wherein said second and fourth N-channelMOS transistors are formed in the second P-type well region whosediffusion layer has no bent portions while letting the layout directionbe parallel to the boundary with respect to the first N-well region withthe first and second P-channel MOS transistors formed therein.

[0007] The diffusion layer is arranged to have its outer shape thatmainly consists of straight line segments including the longest straightline portion which lies parallel to the boundary with respect to thefirst n-well region with the first and second P-channel MOS transistorsformed therein, and simultaneously in the case of defining a straightline acting as the center line extending parallel to such boundary, thelongest line portion is in linear symmetry with such center line; thesecond and fourth N-channel MOS transistors are formed in the secondP-well region whose diffusion layer is mainly arranged by straight linesegments including its longest straight line portion that is parallel tothe boundary with respect to the first n-well region with the first andsecond P-channel MOS transistors formed therein while allowing, whendefining a straight line for use as the center line extending parallelto such boundary, the line portion to be linearly symmetrical with thecenter line. At this time, in the case of employing the linearsymmetrization scheme, complete linear symmetry will not always berequired; alternatively, slight nonsymmetry may also be permissible on acase-by-case basis, which nonsymmetry results from modifying thediffusion layer to have a shape with its portions on the right and leftsides of the center line being substantially the same in area as eachother by way of example.

[0008] In accordance with another aspect of this invention, a firstpolycrystalline silicon lead layer for use as the gate of said thirdN-channel MOS transistor and a second polycrystalline silicon lead layerfor use as the gate of said first P-channel MOS transistor and also asthe gate of said first N-channel MOS transistor are disposed in parallelto each other, wherein a third polycrystalline silicon lead layer foruse as the gate of said fourth N-channel MOS transistor and a fourthpolycrystalline silicon lead layer for use as the gate of said secondN-channel MOS transistor and also as the gate of said second P-channelMOS transistor are disposed in parallel to each other, and wherein thefirst and third polycrystalline silicon lead layers are connected via acontact to a second layer of metal lead layer constituting word lines.

[0009] In accordance with a further aspect of the invention, the inputterminal of said first inverter and the output terminal of said secondinverter may be electrically connected together at a contact whereas theinput terminal of said second inverter and the output terminal of saidfirst inverter are electrically connected together at a contact.

[0010] In accordance with yet another further aspect of the invention, apower supply line connected to the first and second bit lines and thesources of said first and second P-channel MOS transistors and a groundline connected to the sources of said first and second N-channel MOStransistors may be formed of a third layer of metal lead layer lyingparallel to a diffusion layer.

[0011] In accordance with a still another aspect of the invention, thefirst bit line formed of said third layer of metal lead layer may bearranged so that it is between a power supply line formed of said thirdlayer of metal lead layer and a ground line as connected to the sourceof said first N-channel MOS transistor formed of said third layer ofmetal lead layer whereas the second bit line formed of said third layerof metal lead layer is between a power supply line formed of said thirdlayer of metal lead layer and a ground line as connected to the sourceof said second N-channel MOS transistor formed of said third layer ofmetal lead layer.

[0012] In accordance with another further aspect of the invention, thefirst and second bit lines and a power supply line connected to thesources of said first and second P-channel MOS transistors may be formedof a second layer of metal lead layer, wherein word lines are formed ofa third layer of metal lead layer, and wherein a ground line connectedto the sources of said first and second N-channel MOS transistors isformed of the third layer and second layer of metal lead layer.

[0013] In accordance with a still another further aspect of theinvention, memory cells are laid out into the form of an array, whereincontacts to a substrate of P-type well region and a contact to asubstrate of N-type well region are linearly disposed within the arrayand at upper and lower portions of the array in a direction parallel tothe word lines. Although the above is an example which causes twoseparate P-well to be disposed on the opposite sides of an N-wellregion, two N-well regions may be disposed on the opposite sides of ap-well region when the need arises.

[0014] In accordance with yet another further aspect of the invention, asemiconductor device is provided which comprises a plurality of memoryarrays each including an array of memory cells each having at least apair of N-type well region and P-type well region, and at least oneintermediate region between the memory arrays, wherein the N-type wellregion and P-type well region defines therebetween a boundary with atleast one straight line portion, and wherein a diffusion layer is formedin each of the P-type well region and P-type well region to have aplanar shape of either (1) a shape of rectangle having long sidesextending parallel to said straight line portion or (2) a shaperesulting from letting a plurality of rectangles having long sidesextending parallel to the straight line portion be combined together viarespective short sides thereof; or alternatively,

[0015] (1) a shape of rectangle having long sides parallel to saidstraight line portion or (2) a shape resulting from letting a pluralityof rectangles having long sides parallel to said straight line portionbe combined together causing them to extend in the direction of thestraight line.

[0016] At least in memory array regions, bit lines are laid out in adirection parallel to the straight line portion whereas word lines aredisposed in a direction perpendicular to the straight portion.Preferably, in the intermediate region, at least one type of electricallead is railed in a direction at right angles to the straight portion,and a lead (e.g. contact) is also formed which is for making electricalcontact between a power supply voltage lead and the diffusion layer asformed in the N-well region or P-well region. This lead may include apower supply lead, ground lead, or other potential leads.

[0017] The invention is particularly useful for those semiconductormemory devices having static RAM memory cells each consistingessentially of six separate transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a diagram showing an SRAM cell in accordance withEmbodiment 1 of the present invention, for explanation of a layoutpattern of those contacts for connection between MOS transistors andthose for connecting between MOS transistors and metal lead layers.

[0019]FIG. 2 is a diagram showing a layout of via holes of SRAM cellsfor connection between multilayered metal leads in accordance withEmbodiment 1 of this invention

[0020]FIG. 3 is a diagram showing a layout of memory cells and theirassociated peripheral circuitry in accordance with Embodiment 2 of theinvention.

[0021]FIG. 4 is a diagram showing an SRAM cell in accordance withEmbodiment 3 of the invention, for explanation of a layout of thosecontacts for connection between MOS transistors and thosoe forconnection between MOS transistor and metal lead layers.

[0022]FIG. 5 is a diagram showing a layout of via holes of SRAM cellsfor connection between multilayered metal leads in accordance withEmbodiment 3 of the invention.

[0023]FIG. 6 is a diagram showing an SRAM cell in accordance withEmbodiment 4 of the invention, for explanation of a layout of thosecontacts for connection between MOS transistors and those for connectionbetween MOS transistors and metal lead layers.

[0024]FIG. 7 is a diagram showing a layout of via holes of SRAM cellsfor connection between multilayered metal leads in accordance withEmbodiment 3 of the invention.

[0025]FIG. 8 is a diagram showing an SRAM cell in accordance withEmbodiment 5 of the invention, for explanation of a layout of thosecontacts for connection between MOS transistors and those for connectionbetween MOS transistors and metal lead layers.

[0026]FIG. 9 is a diagram showing a layout of via holes of SRAM cellsfor connection between multilayered metal leads in accordance withEmbodiment 5 of the invention.

[0027]FIG. 10 is a diagram showing an SRAM cell in accordance withEmbodiment 6 of the invention, for explanation of a layout of thosecontacts for for connection between MOS transistors and those forconnection between MOS transistors and metal lead layers.

[0028]FIG. 11 is a diagram showing a layout of via holes of SRAM cellsfor connection between multilayered metal leads in accordance withEmbodiment 6 of the invention.

[0029]FIGS. 12a to 12 f are diagrams illustrating in cross-section someof major process steps in the manufacture of the semiconductor device inaccordance with Embodiment 6 of the invention.

[0030]FIG. 13 is a diagram showing an SRAM cell in accordance withEmbodiment 7 of the invention, for explanation of a layout of thosecontacts for connection between MOS transistors and those for connectionbetween MOS transistors and metal lead layers.

[0031]FIG. 14 is a diagram showing a layout of via holes of SRAM cellsfor use in connecting between multilayered metal leads in accordancewith Embodiment 7 of the invention.

[0032]FIG. 15 is a diagram showing an SRAM cell in accordance withEmbodiment 8 of the invention, for explanation of a layout of thosecontacts for connection between MOS transistors and those for connectionbetween MOS transistors and metal lead layers.

[0033]FIG. 16 is a diagram showing a layout of via holes of SRAM cellsfor connection between multilayered metal leads in accordance withEmbodiment 8 of the invention.

[0034]FIG. 17 is a sectional view of a semiconductor device inaccordance with Embodiment 8 of the invention.

[0035]FIGS. 18a to 18 f are diagrams illustrating in cross-section someof major process steps in the manufacture of a semiconductor device inaccordance with Embodiment 9 of the invention.

[0036]FIGS. 19a to 19 g are diagrams illustrating in cross-section someof major process steps in the manufacture of a semiconductor device inaccordance with Embodiment 10 of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

[0037] Several preferred embodiments of the semiconductor memory devicein accordance with the present invention will be explained withreference to the accompanying drawings below.

[0038] <Embodiment 1>

[0039] Referring to FIGS. 1 and 2, there is shown an SRAM cell layout MCembodying the invention. FIG. 1 illustrates well regions and diffusionlayers plus polycrystalline silicon interconnect lead layer as well ascontacts, all of which are formed in or over a semiconductor substratewhereas FIG. 2 depicts a first layer of metal lead layer, via holes 1,second layer of metal lead layer, via holes 2, and a third layer ofmetal lead layer. Symbols used in FIGS. 1 and 2 are indicated at lowerpart of FIG. 2.

[0040] An N-channel type MOS transistor TN1 formed in a P-typesemiconductive well region PW1 and a P-channel type MOS transistor TP1formed in an N-type well region NW1 constitute an inverter INV1. Inaddition, an N-channel MOS transistor TN2 formed in P-type well regionPW2 and a P-channel MOS transistor TP2 formed in N-type well region NW1constitute an inverter INV2.

[0041] An output node of the inverter INV1 is electrically connected bya contact SC1 to an input node of the inverter INV2. An output of theinverter INV2 is electrically connected via a contact SC2 to an input ofthe inverter INV1.

[0042] An N-channel MOS transistor TN3 has a drain electrode connectedto a bit line BL1, a source electrode connected to a drain of theN-channel MOS transistor TN1, and a gate electrode connected to a wordline WD. Similarly an N-channel MOS transistor TN4 has a drain electrodeconnected to a bit line BL2, a source electrode connected to a drain ofthe N-channel MOS transistor TN2, and a gate electrode connected to wordline WD.

[0043] The N-channel MOS transistor TN1 and N-channel MOS transistor TN3are formed over a diffusion layer LN1 whereas the N-channel MOStransistor TN2 and N-channel MOS transistor TN4 are formed over adiffusion layer LN2. The P-channel MOS transistor TP1 is formed over adiffusion layer LP1 whereas the P-channel MOS transistor TP2 is formedover a diffusion layer LP2.

[0044] As the diffusion layers (LN1, LN2, LP1, LP2) are straight lineswith no curved portions, any pattern correction at folded portions is nolonger necessary, resulting in the balance between nodes being improved.In case memory cells are laid out into the form of an array, thediffusion layers become four separate straight lines extending parallelto the bit lines (BL1, BL2).

[0045] In addition, a polycrystalline silicon interconnect lead layerFG3 for use as the gate electrode of the N-channel MOS transistor TN3and a polycrystalline silicon lead layer FG4 for use as the gateelectrode of N-channel MOS transistor TN4 are connected to word lines WLwhich are formed of the second metal lead layer in a vertical directionto the bit lines (BL1, BL2). A polycrystalline silicon interconnect leadlayer FG1 for use as the gate electrodes of the N-channel MOS transistorTN1 and P-channel MOS transistor TP1 and a polycrystalline siliconinterconnect lead layer FG2 for use as the gate electrode of theN-channel MOS transistor TN2 and P-channel MOS transistor TP2 plus thepolycrystalline silicon lead layers (FG3, FG4) are disposed in parallelto the word lines.

[0046] The N-channel MOS transistor TN1 has its source electrodeconnected to a ground potential line Vss1 that is formed of the thirdlayer of metal lead layer whereas a source electrode of the N-channelMOS transistor TN2 is connected to a ground line Vss2 as formed of thethird layer of metal lead layer. In addition, source electrodes of theP-channel MOS transistors (TP1, TP2) are connected to a power supplyvoltage line Vcc1 which is formed of the third layer of metal leadlayer.

[0047] The bit line BL1 is located midway between the power supplyvoltage line Vcc1 and ground line Vss1 whereas bit line BL2 is betweenthe supply voltage line Vcc1 and ground line Vss2. This structure makesit possible to reduce cross-couple noises occurring between bit lines,which advantageously lowers voltages while increasing operation speeds.

[0048] In addition, it is considered that, in case a contact is formedon an n⁻ layer through partial cutaway of side spacers during etching ofcontact holes, a leakage current from the contact via the n⁻ layer tothe substrate may be produced. When a contact is formed for connectionbetween a polycrystalline silicon lead layer and a diffusion layer, adistance between the diffusion layer LP2 and polycrystalline siliconlead layer FG1 should be greater than the length of a side spacer tothereby eliminate formation an n⁻ layer on the polycrystalline siliconlead layer FG1 side of the diffusion layer LP2, which in turn makes itpossible to prevent a flow of leakage current.

[0049] <Embodiment 2>

[0050] Turning to FIG. 3, there is shown an exemplary case where thememory cells MC of Embodiment 1 are laid out into the form of an array.Symbols used herein are the same as those indicated at lower part ofFIG. 2.

[0051] The memory cells MC are organized into an array of 256 rows and128 columns, by way of example. In view of the fact that these memorycells in Embodiment 1 are less in length in the longitudinal directionof bit lines, a total length of such 256 rows of memory cells along thebit lines is shorter than that of prior art devices, thus increasingresultant operation speeds. Neighboring memory cells MC are disposed inlinear symmetry with respect to a “y” axis whereas upper and loweradjacent memory cells MC are in linear symmetry with an “x” axis. Inaddition, specified regions ST for use in supplying more than one powersupply voltage to the substrate are formed at intermediate part of thearray in such a manner that the regions ST extend parallel to word linesWD. One example is that the regions ST are laid out in units of 32-rowgroups. Another example is that regions ST are disposed in units of64-row groups.

[0052] An electrical lead Vbn for supplying a voltage potential to theP-well regions (PW1, PW2) and a lead Vbp for supplying a voltage to theN-well region NW1 are formed to lie parallel to word lines. The lead Vbnmay be coupled to ground potential Vss or, alternatively, any voltagemay be applied thereto which is potentially different from ground Vss.The lead Vbp may be coupled to the power supply voltage Vcc or,alternatively, any voltages potentially different from Vcc may beapplied thereto.

[0053] Note that in each region ST, a power supply voltage line Vcc forpotentially “reinforcing” a power supply voltage line Vcc1 is formed inparallel to word lines while letting a ground potential line Vss forpotentially reinforcing ground potentials (Vss1, Vss2) is formed inparallel to the word lines.

[0054] Also note that the ground lines (Vss1, Vss2) are disposed in adirection perpendicular to the word lines WD whereby upon selecting of asingle word line a voltage potential is supplied from the pair of groundlines to a respective one of those memory cells operatively associatedwith this selected word line so that any possible noises occurring atsuch voltage lines are reduced to thereby advantageously speed up anaccess operation while potentially reducing any voltages concerned.

[0055] Furthermore, the memory cells MC used are great in width in theword line direction so that the layout design of sense amplifiers AMP ismade easier to thereby avoid a need to lay out one sense amplifier fortwo adjacent columns of memory cells, which in turn makes it possible topermit one sense amplifier to be laid out at each column. Additionally aword line driver circuit wddrv becomes flat in layout as compared toprior known ones.

[0056] <Embodiment 3>

[0057]FIGS. 4 and 5 show a SRAM cell layout MC2 in accordance withEmbodiment 3. Symbols as used in FIGS. 4-5 are the same as those in FIG.2. Memory cell MC2 of Embodiment 3 is similar to the memory cell MC ofEmbodiment 1, except that whereas in Embodiment 1 the diffusion layer(LN1, LN2) is formed into a “IT”-like planar shape, which resembles aJapanese battledore plate called “hagoita,” the diffusion layer (LN3,LN4) of Embodiment 4 is of a rectangular shape, and that the contacts(SC1, SC2) are replaced with contacts (SC3, SC4) in the first layer ofmetal lead layers (M11, M12).

[0058] To attain stability, memory cells are typically designed so thatthe gate width of N-channel MOS transistors (TN1, TN2) is one and a halftimes greater than that of N-channel MOS transistors (TN3, TN4) However,in this case, the shape of diffusion layers resembles a T- like planarshape as has been shown in Embodiment 1, which in turn requires extratechniques including pattern correction procedures such as opticalproximity effect correction (OPC) processes. Additionally this wouldresult in degradation of the balance between transistors. In contrast,Embodiment 3 is such that the diffusion layers (LN3, LN4) are designedto have a rectangular shape whereby the micro-patterning requiredbecomes easier while at the same time enabling improvement in balancebetween transistors. Note however that the resultant gate width ratiobecomes as large as 1.0 time, which in turn requires that the so-calledcell ratio be increased by making different drivabilities therebetween,which is achievable by letting the N-channel MOS transistors (TN3, TN4)be greater in oxide film thickness than N-channel MOS transistors (TN1,TN2), or by increasing the gate length thereof, or alternatively byincreasing the threshold value, or still alternatively by lowering theimpurity concentration of lightly-doped drain regions for relaxation ofelectric fields.

[0059] In addition, Embodiment 3 is arranged to employ a contact SC3 anda first layer of metal lead layer M11 in place of the contact SC1 usedin Embodiment 1 for connection between the output of inverter INV1 andthe input of inverter INV2. With such an arrangement, any curved or bentcontacts are no longer necessary, thereby avoiding the need for patterncorrection (OPC) or the like.

[0060] <Embodiment 4>

[0061]FIGS. 6 and 7 show an SRAM cell layout MC3 in accordance with anembodiment 4. Symbols as used in FIGS. 6-7 are the same as those in FIG.2. Memory cell MC3 of Embodiment 4 is similar to the memory cell MC2 ofEmbodiment 3 except that polycrystalline silicon lead layers (FG5, FG6,FG7, FG8) are designed to have a rectangular planar shape. With thiscell, any bent/folded portions are absent thus removing the need for anyadditional pattern correction procedures including OPC processes, whichin turn improves the balance between transistors.

[0062] <Embodiment 5>

[0063]FIGS. 8 and 9 show an SRAM cell layout MC4 in accordance withEmbodiment 5. An explanation on those symbols used in FIGS. 8 and 9 isgiven at lower part of FIG. 8. Memory cell MC4 of Embodiment 5 isdifferent in lead structure from the memory cell MC of Embodiment 1.

[0064] Bit lines (BL3, BL4) and power supply line Vcc2 are formed by useof a second layer of metal lead layer. A word line WD1 and ground lines(Vss5, Vss6) are formed using a third layer of metal lead layer in aperpendicular direction to the bit lines. Ground lines (Vss3, Vss4) areformed using a fourth layer of metal lead layer in a direction parallelto the bit lines.

[0065] A global bit line GB is the electrical interconnect lead that isused in case bit lines are of a hierarchical configuration. The globalbit line GB and bit lines (BL3, BL4) are shielded by the third layer ofmetal lead layer, thus enabling prevention of any possible cross-couplenoises. Additionally the use of ground lines (Vss3, Vss4) makes itpossible to prevent occurrence of cross-couple noises between global bitlines GB.

[0066] <Embodiment 6>

[0067]FIGS. 10 and 11 show an SRAM cell layout MC5 in accordance with anembodiment 6. An explanation as to those symbols used in FIGS. 10-11 isgiven at lower part of FIG. 11. Memory cell MC5 of Embodiment 6 isdifferent from the memory cell MC of Embodiment 1 in structure of theso-called three-layered contacts, each of which is for connectionbetween a gate electrode and its associated diffusion layer.

[0068] Although in Embodiment 1 a gate electrode is connected to adiffusion layer via “L”-like contacts SC1, SC2, Embodiment 6 is arrangedso that the gate electrode is connected to the diffusion layer viasilicide in connect regions SS1, SS2. This makes it unnecessary to bendor curve the individual contact into the L-like shape in order toconnect the gate electrode to the diffusion layer, which in turn makesit possible to provide “I”-like rectangular contacts SC5, SC6. Nofolded/bent portions are present in the contacts used, which eliminatesthe need for pattern correction (OPC).

[0069] One practically implementable flow of some major process steps inthe manufacture of a device structure employing the connect regions SS1,SS2 each for connection between a gate electrode and a diffusion layerassociated therewith via silicide is shown in FIGS. 12a through 12 f.Note here that FIGS. 12a-12 f are cross-sectional views each indicatinga profile as taken along line A-A′ in FIG. 10, with its right sidecorresponding to the side “A” and with left side corresponding to “A′.”

[0070] Fabricate a gate electrode FG made of a chosen polycrystallinesilicon material (see FIG. 12a).

[0071] Form a heavily-doped diffusion layer PM of a specifiedconductivity type-here, P type (FIG. 12b).

[0072] Form side spacers made of silicon nitride (SiN) by chemical vapordeposition (CVD) techniques, on sidewalls of the resultant gateelectrode FG (FIG. 12c).

[0073] Make use of a resist RG to etch away only one of the SiN sidespacers which resides on an active region side under a prespecifiedcondition that enables etching treatment of a silicon nitride film andoxide film at increased selectivity (FIG. 12d).

[0074] Fabricate a heavily-doped P (P+) type diffusion layer P+.

[0075] After having removed through etching certain part of the oxidefilm SiO that lies in the active region that is not covered by anyoverlying gate electrode FG, deposit a high-melting-point metal such asrefractory metal including, but not limited to, cobalt (Co); then,anneal the resultant structure to thereby selectively form silicide onthe poly-silicon gate electrode and diffusion layer (FIG. 12f). At thistime the gate electrode's sidewall and diffusion layer are connectedtogether by such silicide.

[0076] <Embodiment 7>

[0077]FIGS. 13 and 14 show an SRAM cell layout MC6 in accordance withEmbodiment 7. An explanation of those symbols used in FIGS. 13-14 is thesame as that given at lower part of FIG. 11. Memory cell MC6 ofEmbodiment 7 is similar to the memory cell MC5 of Embodiment 6 with thecontacts (SC5, SC6) being replaced with contacts (SC7, SC8) in the firstlayer of metal lead layers (M11, M12).

[0078] With Embodiment 7, all of the contacts used therein are capableof being designed to have a square planar shape, thus avoiding the needfor pattern correction (OPC).

[0079] <Embodiment 8>

[0080]FIGS. 15 and 16 show an SRAM cell layout MC7 in accordance withEmbodiment 8. An explanation of those symbols used in FIGS. 15-16 isgiven at lower part of FIG. 16. Memory cell MC7 of Embodiment 8 issimilar to the memory cell MC of Embodiment 1 with the contacts (SC1,SC2) being replaced with local interconnect nodes (LI1, LI2) and alsowith the word lines being modified in such a manner that these areformed in the first layer of metal lead layer rather than in the secondlayer of metal lead layer while also modifying the bit lines and powersupply and ground lines from the third layer of metal lead layer to thesecond layer of metal lead layer. FIG. 17 depicts a sectional view takenalong line A-B of FIGS. 15-16.

[0081] Embodiment 1 suffers from limitations as to an inability todispose the first layer of metal leads over the contacts SC1, SC2 due tothe fact that these contacts SC1, SC2 are formed of the same layer asthe remaining contacts used. In contrast, Embodiment 8 is specificallyarranged to employ the local interconnect nodes LI1, LI2 formed in aseparate layer from the contacts, thus making it possible to dispose thefirst layer of metal lead layer at upper part, which in turn makes itpossible to reduce by one the requisite number of metal lead layers whencompared to Embodiment 1.

[0082] <Embodiment 9>

[0083] A process flow of major steps in the manufacture of a three-layercontact section of Embodiment 9 is shown in FIGS. 18a-18 f. Thisembodiment 9 is an example of the process for fabrication of thethree-layer contact section as used in Embodiments 1, 3-5 and 8.

[0084] Modern LSIs in recent years are typically designed so thatmicropatterning is done to form contact holes by high-selectivityetching techniques with a silicon nitride film or else used as a stopperto ensure that any unwanted over-etching occurs at filed oxide filmseven when contacts are offset in position from diffusion layers and/orgate electrodes due to the presence of possible alignment errors duringphotolithographical patterning processes. In cases gate electrodes areformed to have reduced electrical resistivities by use of the so-calledsalicide processes, it is possible to obtain the intended electricalconduction between a contact lying over a gate electrode and a contactoverlying a diffusion layer even when the both contacts are fabricatedat a time because of the fact that the contact holes required arefabricated after completion of a procedure having the steps of formingsilicide through exposure of selected portions overlying diffusionlayers and gate electrodes after having formed such diffusion layers,depositing thereover a silicon nitride film for use as an etchingstopper, and then further depositing thereover an interlayer dielectricfilm. On the contrary, in the case of either traditionally widelyemployed polycide gate electrodes or polymetal gate electrodes that havebeen developed and announced recently, residual portions of aninsulative film such as oxide film can overlie gate electrodes therebypreventing exposure of these gate electrodes prior to deposition of asilicon nitride film acting as the etch stopper; accordingly, wheneveran attempt is made to form the intended contacts through deposition of asilicon nitride film thereover, the oxide film behaves to partly resideat the bottom of a respective one of those contacts overlying the gateelectrodes, which makes it impossible or at least greatly difficult toprovide electrical conduction required. Embodiment 9 is for enablingachievement of electrical conduction of such contacts overlying gateelectrodes by previous removal of any silicon nitride film portionsoverlying gate electrodes at specified part whereat contact holes willbe defined.

[0085] An explanation will now be given of the process flow in themanufacture of Embodiment 9 with reference to FIGS. 18a-18 f below.

[0086] After having fabricated a gate electrode and a diffusion layerP+, deposit a silicon nitride film SiN for use as an etch stopper (FIG.18a). The gate electrode is a lamination of polycrystalline siliconPolySi and tungsten W, with an oxide film SiO being further multilayeredthereon as a protective film.

[0087] Remove by dry etching techniques specified part of the siliconnitride film at locations for definition of a contact hole overlying thegate electrode (FIG. 18b).

[0088] Deposit a TEOS film and others by plasma CVD methods to therebyform an interlayer dielectric film (FIG. 18c).

[0089] Let a selected portion of the oxide film at a contact openingportion be etched away by high selective dry etching techniques (FIG.18d). Owing to such high selective etching, the silicon nitride filmremains free from etch treatment and thus acts as a stopper. Since thereis no stopper at the portion overlying the gate electrode from which thesilicon nitride film has been removed away in advance, such portion willbe fully etched to the upper part of the gate electrode. This permitselectrical conduction on the gate electrode also.

[0090] Remove the silicon nitride film by dry etching techniques (FIG.18e). Deposit a chosen metal such as tungsten in the resulting contacthole, thereby forming a buried plug (FIG. 18f).

[0091] <Embodiment 10>

[0092] Turning to FIGS. 19a-19 g, there is shown a process flow in themanufacture of the three-layer contact section of Embodiment 10.Embodiment 10 is one example of the process for forming the three-layercontact section of Embodiments 1, 3-5 and 8.

[0093] A difference of the process flow of Embodiment 10 from that ofEmbodiment 9 is that more than one portion of the oxide film at aspecified location whereat a contact hole is to be opened over the gateelectrode has been removed in advance prior to deposition of a siliconnitride film for use as the etch stopper.

[0094] The fabrication process flow of Embodiment 10 will be explainedwith reference to FIGS. 19a-19 g below.

[0095] Fabricate a gate electrode and a diffusion layer P+ (FIG. 19a).The gate electrode is a lamination of polycrystalline silicon PolySi andtungsten W, with an oxide film SiO further stacked thereon as aprotective film.

[0096] Remove by dry etching techniques a specified part of the siliconnitride film at the location for definition of a contact hole overlyingthe gate electrode, thus letting the gate electrode be exposed at itsupper part (FIG. 19b).

[0097] Deposit a silicon nitride film SiN as an etch stopper (FIG. 19c).

[0098] Deposit a TEOS film or else by plasma CVD methods to thereby forman interlayer dielectric film (FIG. 19d).

[0099] Let a portion of the oxide film at contact opening portion beetched away by high selective dry etching techniques (FIG. 19e). Due tosuch high selective etching, the silicon nitride film remains free frometching treatment and thus acts as the stopper. Remove the siliconnitride film by dry etching techniques (FIG. 19f). A certain portionfrom which the oxide film overlying the gate electrode has been removedprior to deposition of the silicon nitride film is thus exposed at thistime, which permits electrical conduction on the gate electrode also.

[0100] Deposit a chosen metal such as tungsten in the resultant contacthole, thereby forming a buried plug (FIG. 19g).

[0101] In accordance with the embodiments stated above, any diffusionlayers used therein are specifically designed to have a simplifiedplanar shape excluding unnecessarily complicated shapes, which may inturn facilitate micro-patterning processes.

1. A semiconductor memory device comprising a first inverter including afirst N-channel metal oxide semiconductor (MOS) transistor and a firstP-channel MOS transistor, a second inverter including a second N-channelMOS transistor and a second P-channel MOS transistor with an inputterminal being connected to an output terminal of said first inverterand with an output terminal being connected to an input terminal of saidfirst inverter, a third N-channel MOS transistor having a sourceconnected to the output terminal of said first inverter and a drainconnected to a first bit line and also a gate connected to a word line,and a fourth N-channel MOS transistor having a source connected to theoutput terminal of said second inverter and a drain connected to asecond bit line plus a gate connected to a word line, wherein the firstand third N-channel MOS transistors are formed in a first P-type wellregion, its diffusion layer having an outer shape consisting essentiallyof straight lines including a straight line portion with a maximallength extending parallel to a boundary relative to a first N-type wellregion with the first and second P-channel MOS transistors formedtherein and also being linear symmetrical with respect to a straightline defined as a center line extending parallel to the boundary, andwherein the second and fourth N-channel MOS transistors are formed in asecond P-type well region, its diffusion layer having an outer shapeconsisting essentially of straight lines including a straight lineportion with a maximal length extending parallel to the boundaryrelative to the first n-type well region with said first and secondP-channel MOS transistors formed therein and also being linearsymmetrical with the straight line defined as the center line inparallel to the boundary.
 2. A semiconductor memory device according toclaim 1, wherein a first polycrystalline silicon lead layer for use asthe gate of said third N-channel MOS transistor and a secondpolycrystalline silicon lead layer for use as the gate of said firstP-channel MOS transistor and also as the gate of said first N-channelMOS transistor are disposed in parallel to each other, wherein a thirdpolycrystalline silicon lead layer for use as the gate of said fourthN-channel MOS transistor and a fourth polycrystalline silicon lead layerfor use as the gate of said second N-channel MOS transistor and also asthe gate of said second P-channel MOS transistor are disposed inparallel to each other, and wherein the first and third polycrystallinesilicon lead layers are connected via a contact to a second layer ofmetal lead layer constituting word lines.
 3. A semiconductor memorydevice according to claim 1, wherein the input terminal of said firstinverter and the output terminal of said second inverter areelectrically connected together at a contact whereas the input terminalof said second inverter and the output terminal of said first inverterare electrically connected together at a contact.
 4. A semiconductormemory device according to claim 1, wherein a power supply lineconnected to the first and second bit lines and the sources of saidfirst and second P-channel MOS transistors and a ground line connectedto the sources of said first and second N-channel MOS transistors areformed of a third layer of metal lead layer lying parallel to adiffusion layer.
 5. A semiconductor memory device according to claim 4,wherein the first bit line formed of said third layer of metal leadlayer is between a power supply line formed of said third layer of metallead layer and a ground line as connected to the source of said firstN-channel MOS transistor formed of said third layer of metal lead layerwhereas the second bit line formed of said third layer of metal leadlayer is between a power supply line formed of said third layer of metallead layer and a ground line as connected to the source of said secondN-channel MOS transistor formed of said third layer of metal lead layer.6. A semiconductor memory device according to claim 1, wherein the firstand second bit lines and a power supply line connected to the sources ofsaid first and second P-channel MOS transistors are formed of a secondlayer of metal lead layer, wherein word lines are formed of a thirdlayer of metal lead layer, and wherein a ground line connected to thesources of said first and second N-channel MOS transistors is formed ofthe third layer and second layer of metal lead layer.
 7. A semiconductormemory device according to claim 1, wherein a memory cell is constitutedfrom said first inverter and said second inverter plus said thirdN-channel MOS transistor as well as said fourth N-channel MOStransistor, wherein memory cells each similar in configuration to saidmemory cell are laid out in form of an array, and wherein contacts to asubstrate of P-type well region and a contact to a substrate of N-typewell region are linearly disposed within the array and at upper andlower portions of the array in a direction parallel to the word lines.8. A semiconductor memory device according to claim 2, wherein a memorycell is constituted from said first inverter and said second inverterplus said third N-channel MOS transistor as well as said fourthN-channel MOS transistor, wherein memory cells each similar inconfiguration to said memory cell are laid out in form of an array, andwherein contacts to a substrate of P-type well region and a contact to asubstrate of N-type well region are linearly disposed within the arrayand at upper and lower portions of the array in a direction parallel tothe word lines.
 9. A semiconductor memory device according to claim 3,wherein a memory cell is constituted from said first inverter and saidsecond inverter plus said third N-channel MOS transistor as well as saidfourth N-channel MOS transistor, wherein memory cells each similar inconfiguration to said memory cell are laid out in form of an array, andwherein contacts to a substrate of P-type well region and a contact to asubstrate of N-type well region are linearly disposed within the arrayand at upper and lower portions of the array in a direction parallel tothe word lines.
 10. A semiconductor memory device according to claim 4,wherein a memory cell is constituted from said first inverter and saidsecond inverter plus said third N-channel MOS transistor as well as saidfourth N-channel MOS transistor, wherein memory cells each similar inconfiguration to said memory cell are laid out in form of an array, andwherein contacts to a substrate of P-type well region and a contact to asubstrate of N-type well region are linearly disposed within the arrayand at upper and lower portions of the array in a direction parallel tothe word lines.
 11. A semiconductor memory device according to claim 5,wherein a memory cell is constituted from said first inverter and saidsecond inverter plus said third N-channel MOS transistor as well as saidfourth N-channel MOS transistor, wherein memory cells each similar inconfiguration to said memory cell are laid out in form of an array, andwherein contacts to a substrate of P-type well region and a contact to asubstrate of N-type well region are linearly disposed within the arrayand at upper and lower portions of the array in a direction parallel tothe word lines.
 12. A semiconductor memory device according to claim 6,wherein a memory cell is constituted from said first inverter and saidsecond inverter plus said third N-channel MOS transistor as well as saidfourth N-channel MOS transistor, wherein memory cells each similar inconfiguration to said memory cell are laid out in form of an array, andwherein contacts to a substrate of P-type well region and a contact to asubstrate of N-type well region are linearly disposed within the arrayand at upper and lower portions of the array in a direction parallel tothe word lines.
 13. A semiconductor memory device comprising: a firstinverter having a first N-channel MOS transistor and a first P-channelMOS transistor; a second inverter having a second N-channel MOStransistor and a second P-channel MOS transistor with an input terminalbeing connected to an output terminal of said first inverter and with anoutput terminal being connected to an input terminal of said firstinverter; a third N-channel MOS transistor having a source connected tothe output terminal of said first inverter, a drain connected to a firstbit line, and a gate connected to a word line; and a fourth N-channelMOS transistor having a source connected to the output terminal of saidsecond inverter, a drain connected to a second bit line, and a gateconnected to a word line, wherein the first and third N-channel MOStransistors are formed in a first P-type well region, a diffusion layerformed in said first P-type well region has a shape as resulting fromletting a rectangle having long sides in a direction parallel to aboundary relative to a first N-type well region with the first andsecond P-channel MOS transistors formed therein be connected in theparallel direction, the second and fourth N-channel MOS transistors areformed in a second P-type well region, and a diffusion layer formed insaid second P-type well region has a shape as resulting from letting arectangle having long sides in a direction parallel to the boundaryrelative to the first n-type well region with said first and secondP-channel MOS transistors formed therein be connected in the paralleldirection.
 14. A semiconductor device comprising first and secondinverters with an output of each inverter being as an input of aremaining inverter, a first switch connected to a connection nodebetween an output of the first inverter and an input of the secondinverter, and a second switch connected to a connection node between aninput of said first inverter and an output of said second inverter,wherein said semiconductor device has an N-type well region and firstand second P-type well regions as disposed on opposite sides of saidN-type well region, a diffusion layer formed in each of said N-type wellregion and said first and second P-type well regions is arranged inplanar shape to have one of (1) a shape consisting essentially of asingle rectangle having long sides in an elongate direction of aboundary line of said N-type well region and said first and secondP-type well regions and (2) a shape resulting from combination of aplurality of rectangles in the elongate direction of the boundary lineof said N-type well region and said first and second P-well regions, therectangles having long sides in said elongate direction.
 15. Asemiconductor device according to claim 14, wherein the diffusion layerformed in said N-type well region and P-type regions has its planarshape resembling a single rectangle having long sides in the elongatedirection of boundary lines of said N-type well region and said firstand second P-type well regions.
 16. A semiconductor device according toclaim 14, wherein the diffusion layer formed in said N-type well regionor P-type region has its planar shape of a combined form as resultingfrom combination of a first rectangle having long sides in the elongatedirection of boundary lines of said N-type well region and said firstand second P-type well regions along with a short side of a first lengthand a second rectangle having long sides in the elongate direction ofthe boundary lines of said N-type well region and said first and secondP-type well regions along with a short side of a second length, thecombination being in the elongate direction of said boundary lines. 17.A semiconductor device according to claim 9, wherein said first inverteris formed of a first N-channel MOS transistor and a first P-channel MOStransistor as formed using the first P-type well region and N-type wellregion, said second inverter is formed of a second N-channel MOStransistor and a second P-channel MOS transistor as formed using thesecond P-type well region and N-type well region, said first switch isformed of a third N-channel MOS transistor as formed in said firstP-type well region, and said second switch is formed of a fourthN-channel MOS transistor formed in said second P-type well region.
 18. Asemiconductor device according to claim 10, wherein said first inverteris formed of a first N-channel MOS transistor and a first P-channel MOStransistor as formed using the first P-type well region and N-type wellregion, said second inverter is formed of a second N-channel MOStransistor and a second P-channel MOS transistor as formed using thesecond P-type well region and N-type well region, said first switch isformed of a third N-channel MOS transistor as formed in said firstP-type well region, and said second switch is formed of a fourthN-channel MOS transistor formed in said second P-type well region.
 19. Asemiconductor device according to claim 11, wherein said first inverteris formed of a first N-channel MOS transistor and a first P-channel MOStransistor as formed using the first P-type well region and N-type wellregion, said second inverter is formed of a second N-channel MOStransistor and a second P-channel MOS transistor as formed using thesecond P-type well region and N-type well region, said first switch isformed of a third N-channel MOS transistor as formed in said firstP-type well region, and said second switch is formed of a fourthN-channel MOS transistor formed in said second P-type well region.
 20. Asemiconductor device according to claim 17, wherein the first and secondinverters and the first and second switches constitute a static memorycell, wherein a plurality of memory cells each similar in structure tosaid static memory cell are provided to constitute a memory array, andwherein bit lines are disposed parallel to an elongate direction of morethan one boundary line of said N-type well region and said first andsecond P-type well regions whereas word lines are disposed in adirection perpendicular to the boundary line.
 21. A semiconductor deviceaccording to claim 18, wherein the first and second inverters and thefirst and second switches constitute a static memory cell, wherein aplurality of memory cells each similar in structure to said staticmemory cell are provided to constitute a memory array, and wherein bitlines are disposed parallel to an elongate direction of more than oneboundary line of said N-type well region and said first and secondP-type well regions whereas word lines are disposed in a directionperpendicular to the boundary line.
 22. A semiconductor device accordingto claim 19, wherein the first and second inverters and the first andsecond switches constitute a static memory cell, wherein a plurality ofmemory cells each similar in structure to said static memory cell areprovided to constitute a memory array, and wherein bit lines aredisposed parallel to an elongate direction of more than one boundaryline of said N-type well region and said first and second P-type wellregions whereas word lines are disposed in a direction perpendicular tothe boundary line.
 23. A semiconductor memory device according to claim20, wherein said device further comprises a plurality of memory arrayseach similar in structure to said memory array, and an intermediateregion between said memory arrays for causing at least one of a contactto a substrate of P-type well region and a contact to a substrate ofN-type well region to be disposed therein.
 24. A semiconductor memorydevice according to claim 21, wherein said device further comprises aplurality of memory arrays each similar in structure to said memoryarray, and an intermediate region between said memory arrays for causingat least one of a contact to a substrate of P-type well region and acontact to a substrate of N-type well region to be disposed therein. 25.A semiconductor memory device according to claim 22, wherein said devicefurther comprises a plurality of memory arrays each similar in structureto said memory array, and an intermediate region between said memoryarrays for causing at least one of a contact to a substrate of P-typewell region and a contact to a substrate of N-type well region to bedisposed therein.
 26. A semiconductor device according to claim 23,wherein an electrical lead having a specified voltage potential isdisposed within said intermediate region in parallel to said word lines,and wherein said contact is for electrical connection between the leadand the substrate.
 27. A semiconductor device according to claim 24,wherein an electrical lead having a specified voltage potential isdisposed within said intermediate region in parallel to said word lines,and wherein said contact is for electrical connection between the leadand the substrate.
 28. A semiconductor device according to claim 25,wherein an electrical lead having a specified voltage potential isdisposed within said intermediate region in parallel to said word lines,and wherein said contact is for electrical connection between the leadand the substrate.
 29. A semiconductor memory device comprising: aplurality of memory arrays each including an array of memory cells eachhaving at least a pair of N-type well region and P-type well region; atleast one intermediate region between the memory arrays; said N-typewell region and P-type well region defining therebetween a boundary withat least one straight line portion; a diffusion layer formed in each ofsaid P-type well region and P-type well region to have a planar shape ofone of (1) a shape of rectangle having long sides extending parallel tosaid straight line portion and (2) a shape resulting from letting aplurality of rectangles having long sides extending parallel to saidstraight line portion be combined together via respective short sidesthereof; bit lines disposed parallel to said straight line portion alongwith word lines disposed in a direction perpendicular to said straightline portion; and said intermediate region including at least one typeof power supply lead as disposed therein and extending in the directionperpendicular to said straight line portion and also a lead formedtherein for electrical contact between the power supply lead and thediffusion layer as formed in said N-type well region or P-type wellregion.